PIC18F26J50-I/ML【PDF 17/32 页】IC PIC MCU FLASH 64K 2V 28-QFN

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Sheet目录3858

13页 14页 15页 16页 [17页]18页 19页 20页 21页

PIC18F2XJXX/4XJXX FAMILY

DS39687E-page 24

2009 Microchip Technology Inc.

TABLE 5-7:

PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS

Bit Name

Configuration

Words

Description

DEBUG

CONFIG1L

Background Debugger Enable bit

1 = Background debugger disabled, RB6 and RB7 configured as general purpose

I/O pins

0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug

XINST

CONFIG1L

Enhanced Instruction Set Enable bit

1 = Instruction set extension and Indexed Addressing mode enabled

0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)

STVREN

CONFIG1L

Stack Overflow/Underflow Reset Enable bit

1 = Reset on stack overflow/underflow enabled

0 = Reset on stack overflow/underflow disabled

CFGPLLEN

CONFIG1L

Enable PLL on Start-up bit

1 = PLL enabled on start-up. Not recommended for low-voltage designs.

0 = PLL disabled on start-up. Firmware may later enable PLL through OSCTUNE<6>.

PLLDIV<2:0>

CONFIG1L

96 MHz PLL Input Divider bits

Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.

111 = No divide – oscillator used directly (4 MHz input)

110 = Oscillator divided by 2 (8 MHz input)

101 = Oscillator divided by 3 (12 MHz input)

100 = Oscillator divided by 4 (16 MHz input)

011 = Oscillator divided by 5 (20 MHz input)

010 = Oscillator divided by 6 (24 MHz input)

001 = Oscillator divided by 10 (40 MHz input)

000 = Oscillator divided by 12 (48 MHz input)

WDTEN

CONFIG1L

Watchdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled (control is placed on SWDTEN bit)

CP0(4)

CONFIG1H

Code Protection bit

1 = Program memory is not code-protected

0 = Program memory is code-protected

CPDIV<1:0>(3)

CONFIG1H

CPU System Clock Selection bits

11 = No CPU system clock divide

10 = CPU system clock divided by 2

01 = CPU system clock divided by 3

00 = CPU system clock divided by 6

IESO

CONFIG2L(1,2)

Two-Speed Start-up (Internal/External Oscillator Switchover) Control bit

1 = Oscillator Switchover mode enabled

0 = Oscillator Switchover mode disabled

FCMEN

CONFIG2L(1,2)

Fail-Safe Clock Monitor Enable bit

1 = Fail-Safe Clock Monitor enabled

0 = Fail-Safe Clock Monitor disabled

CLKOEC

CONFIG2L

EC Mode Clock Output Enable bit

1 = CLKO output signal active on the RA6 pin (EC mode only)

0 = CLKO output disabled

SOSCSEL<1:0>

CONFIG2L

Secondary Oscillator Circuit Selection bits

11 = High-power SOSC circuit selected

10 = Digital Input mode (SCLKI)

01 = Low-power SOSC circuit selected

00 = Reserved

Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.

2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.

3: These bits are not implemented in PIC18F47J13 family devices.

4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code

protection, perform an ICSP Bulk Erase operation.

5: Not implemented on PIC18F47J53 family devices.

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